1. Field of the Invention
The present invention relates to a data switching apparatus, and more particularly to a communication data switching apparatus for handling packet signal data.
2. Description of the Related Art
One conventional communication data switching apparatus is shown in FIG. 1 of the accompanying drawings. As shown in FIG. 1, the conventional communication data switching apparatus comprises a plurality of receiving circuits 801 for receiving data from input lines, a central processing unit (CPU) 802 for analyzing the header of received data to determine a transmitting circuit to which the data are to be forwarded, and a plurality of transmitting circuits 803 for adding a header and so on to the data transmitted from the receiving circuits 801 and transmitting the data to output lines. The receiving circuits 801, the CPU 802, and the transmitting circuits 803 are interconnected by a data bus 804.
Operation of the conventional communication data switching apparatus shown in FIG. 1 will be described below. A signal received by one of the receiving circuits 801 includes a header in its initial part which represents a destination. The receiving circuit 801 separates the header and transmits the header to the CPU 802. The CPU 802 determines an output line to which data are to be transmitted based on the header given from the receiving circuit 801. The received signal also includes the data following the header. The data are transmitted through the CPU 802 to one of the transmitting circuits 803 which is connected to the output line which has already been determined by the CPU 802. The transmitting circuit 803 adds a new header to the data received from the CPU 802, and transmits the data with the added new header to the output line.
For speeding up the transmission of data from a receiving circuit to a transmitting circuit, Japanese laid-open patent publication No. 63-219248 discloses a process of concurrently receiving data and transmitting a packet simultaneously with the processing of a header.
An output line, i.e., a transmitting circuit, is determined based on the header of a signal received by a receiving circuit, and then data of the signal are transmitted from the receiving signal through a bus to the transmitting circuit. Therefore, if a signal received from an input line is to be transmitted to a plurality of output lines, then it is necessary to transmit the data from the receiving circuit to the transmitting circuit as many times as the number of the output lines.
Though the process disclosed in Japanese laid-open patent publication No. 63-219248 speeds up the transmission of data by concurrently receiving data and transmitting a packet simultaneously with the processing of a header, the disclosed process is required to receive and transmit data with respect to each of the stations which transmit and receive data.
If the disclosed process is employed in a MCA (Multi-Channel Access) system for relaying audio data from one station to a number of stations in digital business radio services, then delays in the relaying of data from an input line to output lines are built up, and the traffic of the bus is impeded.